发明名称 ISOLATING SYSTEM OF VERTICAL SYNCHRONOUS SIGNAL
摘要 PURPOSE:To avoid delivering the signal which is detected by mistake and thus increase the reliability, by detecting the duration of the equivalent pulse and then delivering the vertical synchronous signal when the equivalent pulses are obtained in a prescribed number and within a time set previously. CONSTITUTION:The synchronous signal (a') having the inversed phase is applied to the terminal 1, and the gate pulse (d) of 1/2 the horizontal synchronous signal is applied to the terminal 5. Then the logic product between the signal (a') supplied from the terminals 1 and 2 and the pulse (d) is obtained through the gate 7, and the output pulse (e) is supplied to the pulse duration detector 8. At the same time, the gate pulse (d) is supplied to the detector 8 along with application of the drop-out signal (h) from the terminal 6. Then the pulse (f) is delivered through the detector 8 only when the signal (a') coincides with the equivalent pulse duration to be applied to the counter 9 and the gate pulse generator 10. And the pulses (f) are counted for the period decided by the generator 10, and this count value is judged by the 1st and 2nd decoders 11 and 12. Then the correct vertical synchronous signal (c) is delivered via the pulse delay unit 13.
申请公布号 JPS5650671(A) 申请公布日期 1981.05.07
申请号 JP19790120013 申请日期 1979.09.20
申请人 HITACHI ELECTRONICS 发明人 USUI SHIYUUJI
分类号 H04N5/10;(IPC1-7):04N5/10 主分类号 H04N5/10
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