| 摘要 |
PURPOSE:To obtain a high density semiconductor device by employing two wiring layers of a polysilicon layer and a molybdenum layer for the interconnecting wiring of CMOS type ICs, reducing the sizes of the interconnecting wiring layer, and also reducing the resistance of the interconnecting wiring. CONSTITUTION:A P type well 11, a field oxide film 12, a gate insulating film 13 are formed on a semiconductor substrate 10. Then, a drain contacting hole is formed and a polysilicon layer 15 is formed on all the surface. Thereafter, an SiO2 film is selectively formed, impurities are doped, and drain contacts 26 and 27 are formed, respectively. Then, the SiO2 film is removed, molibdenum layer 18c is formed, and gate layers 15a and 18a and an interconnecting wiring layer are formed by selective etching. Thereafter, a mask layer wherein a hole is provided at the specified portion of the transistor is formed, and source and drain regions are self-aligningly formed by the ion implantation method. |
