发明名称 CLOCK SYNCHRONIZATION SYSTEM BETWEEN SENDER AND RECEIVER IN PACKET NETWORK AND CLOCK SYNCHRONIZATION DEVICE
摘要 PURPOSE:To prevent the effect of fluctuation in a delay in a network in the case of clock synchronization in an asynchronous packet network working on a synchronous network. CONSTITUTION:A transmission data 601 is written in a transmission buffer 603 by using a sender side asynchronous clock 602 and when data by a packet length are stored, a time stamp block 605 expresses a phase of the asynchronous clock 602 of the sender side on the moment in a clock 604 of an asynchronous packet network 608 to obtain a time stamp and a packet generation block 607 generates a packet and sends it. The packet at the receiver side is given to a packet separation block 609, in which the packet is separated into the information part, the time stamp part and the header trailer part, and the data of the information part is written in a reception buffer 601 by using the clock 604, the time stamp part is written in the processing block 611 and the reception clock 613 is corrected based on the time stamp and the clock 604 of the asynchronous packet network to read the data.
申请公布号 JPH0537560(A) 申请公布日期 1993.02.12
申请号 JP19910212772 申请日期 1991.07.29
申请人 NEC CORP 发明人 IWATA ATSUSHI
分类号 H04L7/00;H03L7/14;H04L7/033;H04L12/28;H04L12/70;H04L12/951 主分类号 H04L7/00
代理机构 代理人
主权项
地址