发明名称 FIVE-INPUT ADDER
摘要 PURPOSE:To provide a 5-input adder which shorten the delay of a critical path. CONSTITUTION:The 5-input adder 10 has five input signals 14-18, two carry input signals 19 and 110, two carry output signals 111 and 112, one carry signal 114, and one sum signal 113. One of the carry output signals is a function of five input signals. The other carry output signal is a function of the five input signals and one carry input signal. The sum signal and carry signals are a function of the five inputs signals and two carry input signals.
申请公布号 JPH0535446(A) 申请公布日期 1993.02.12
申请号 JP19910190427 申请日期 1991.07.31
申请人 NEC CORP 发明人 BENJIYAMIN SHII
分类号 G06F7/50;G06F7/508;G06F7/53;G06F7/533 主分类号 G06F7/50
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