发明名称 |
MONITOR CIRCUIT IN CHANNEL SELECTING STATE OF PARALLEL FRAME SYNCHRONIZATION CIRCUIT |
摘要 |
PURPOSE:To reduce number of monitor pins in the channel selection state independently of number of output channels by using a phase signal corresponding to a frame counter according to a state of a channel selection signal as a monitor signal. CONSTITUTION:A phase signal PH1 (or any of PH2-PHn) given to a decision circuit 9 from a frame counter 8 corresponding to an active signal S1 (or any of S2-Sn) among channel selection signals S1-Sn given from a channel selection circuit 5 to the decision circuit 9 is outputted from a monitor signal terminal 11. Then a frame pulse FP being a reference signal RS is outputted from a reference signal terminal 10. Thus, which of the channel selection signals S1-Sn is active is confirmed by comparing the both. |
申请公布号 |
JPH0537510(A) |
申请公布日期 |
1993.02.12 |
申请号 |
JP19910186291 |
申请日期 |
1991.07.25 |
申请人 |
FUJITSU LTD |
发明人 |
GOTO MASAYUKI;MATSUO HIROYUKI |
分类号 |
H03M9/00;H04J3/06;H04L7/08 |
主分类号 |
H03M9/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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