发明名称 MEMORY CONTROLLER
摘要 PURPOSE:To obtain the memory controller which can shorten a memory check time at the time of system boot strapping. CONSTITUTION:In a regular memory access, a main CPU 13 used a data bus 15, an address bus 21, and a control bus 22, and executes an access to RAM blocks 11-0 to 11-n through address convertion/RAM control parts 34-0 to 34-n, and selector parts 35-0 to 35-n, respectively. On the other hand, at the time of system boot strapping sub-CPUs 32-0 to 32-n provided on every RAM block execute a memory check in parallel with respect to each RAM block through the selector parts 35-0 to 35-n, respectively. The selector parts 35-0 to 35-n select one of the main CPU 13 or the sub-CPUs 32-0 to 32-n.
申请公布号 JPH0535605(A) 申请公布日期 1993.02.12
申请号 JP19910191796 申请日期 1991.07.31
申请人 SANYO ELECTRIC CO LTD 发明人 MIMURA SHUICHI
分类号 G06F11/22;G06F12/16 主分类号 G06F11/22
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