| 摘要 |
PURPOSE:To refresh data stored in memory cells in a low restoration level state by performing 1st refreshing operation right after the end of reading/ writing operation for all the memory cells in a short period. CONSTITUTION:A frequency dividing circuit 106 divides the frequency of clock pulses and a frequency division control circuit 107 varies time-division control pulses when the clock pulses reach a specific quantity. A refreshment address generating means 104 generates a refreshment address corresponding to the output of the frequency division circuit and a control circuit 105 generates a word line activation pulse in response to the output of the frequency division circuit and the control pulses. Then a decoding means 103 selects a memory cell array 101 including plural bit lines and word lines and specific word lines to activate the selected word lines corresponding to a word line activation signal. |
