| 摘要 |
PURPOSE:To provide a memory cell structure which can realize reduction in size to the same degree as SGT and sufficient cell storage capacity with the present process technology. CONSTITUTION:A groove is formed on the surface of a silicon substrate and a switching transistor defining two side surfaces facing with each other as the source and drain is formed on the upper part of a column-wise semiconductor layer 1 separated with the groove. A capacitor is formed with a storage node electrode 5 which is in contact with a side surface as a storage node contact 9 of these two side surfaces and is formed via an insulating film around the other side surface to surround the entire part of a column type semiconductor layer 1 and a plate electrode 6 which is formed via the capacitor insulating film 7 to surround this storage node electrode 5, a bit line contact 10 is formed at the side surface facing the side surface of the column type semiconductor layer forming the storage node contact 9, and moreover a word line 2 is formed on top of the column type semiconductor layer. |
