| 摘要 |
The generator separates the horizontal (fH) and the colour (fsH) synchronous signals from the composite video signal to compare the two signals with each other for the relationship of fsc = 455/ 2 fH when the one signal is equal to the relationship of fsH, the corresponding signal is locked at a phase locked loop (PLL) to generate the main clock. The generator generates main clock for the standard signal. It also reduces the screen noise by removing the bit generated between two clocks.
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