BIT LINE SENSOR AMPLIFIER BALANCE SYSTEM OF DRAM

摘要

The DRAM cell array has a number of bit and word lines and metal shunt regions formed by conductive connection of polysilicon and metal word lines in preset spacing. A first bit line sense amplifier (12) is coupled to first and second bit lines (1,2) adjacent to the metal shunt region (11). A second bit line sense amplifier is fitted at one side of the first bit line amplifier and is coupled to third and fourth bit lines. On the other side of the first bit line sense amplifier is provided a third bit line sense amplifier coupled to fifth and sixth bit lines. The symmetrical structure of the DRAM cell array is formed without the cell size, thereby removing the capacitance asymmetry of the bit line amplifiers.