| 摘要 |
An arithmetic operation processing apparatus in which one or more multipliers and a plurality of multiplicands are inputted, a multiplication result between one multiplier and one multiplicand and a multiplication result between a complement of the one multiplicand and the other multiplier are added together and outputted. The arithmetic operation processing apparatus includes a plurality of selectors each for selectively outputting the one multiplicand or the other multiplicand in accordance with a plurality of control signals generated from the one multiplier; and an adder for adding together outputs from the selectors.
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