| 摘要 |
PURPOSE:To facilitate data buss selection by providing a micro-processor which is capable of selectively designating data transfer which uses the bit width of a data bus terminal up to its maximum, data transfer which dynamically switches partial use and full use of the bit width, and data transfer which uses only a part of the bit width. CONSTITUTION:A sizing latch where designation of a reduction data bus is latched, a bus cycle detector which discriminates whether an additional bus cycle is necessary or not by the state of the bus cycle, a command decoder which drives a bus enable terminal to generate various control signals, data write buffers 114, 115, and 116 which divisionally drive a data bus terminal 122, and a multiplexer MPX117 which selects inputs of operand read registers 0PRH112 and OPRL113 which divisionally latch the state of the data bus terminal 122 are provided. |
