发明名称 MEMORY CONTROL CIRCUIT
摘要 <p>PURPOSE:To provide the memory control circuit in which refresh of the memory does not stop even though a system reset switch is pushed down and the data of the memory is held even though a system reset is generated. CONSTITUTION:A refresh circuit 171 of the memory is initialized with a power on/reset signal 141 being outputted when a power source is turned on and it is not affected with a rest signal 151 being outputted with a reset switch 130. Then even though the system reset switch 130 is pushed down, the refresh of the memory 180 does not stop and the content stored in the memory 180 is held.</p>
申请公布号 JPH0528757(A) 申请公布日期 1993.02.05
申请号 JP19910178025 申请日期 1991.07.18
申请人 CANON INC 发明人 MOBARA YASUHISA
分类号 G06F1/24;G11C11/401;G11C11/406 主分类号 G06F1/24
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