| 摘要 |
<p>PURPOSE:To improve the code error detection accuracy by employing a reverse sequence FSR and a LIFO shift register in addition to a forward sequence FSR outputting a same bit pattern as that of a reception signal to store once a reception signal and employing a reverse sequence PN signal to measure a code error. CONSTITUTION:A reception signal (a) inputted from a system 1 to be tested to an input terminal 7 is inputted to a terminal of a forward sequence FSR 9a via a changeover circuit 8. Simultaneously, a forward sequence PN signal b1 outputted from the FSR9a is inputted to a terminal of an EXOR gate 10a of a comparator circuit 10 and also inputted to the other terminal of the circuit 8. The circuit 8 is controlled by a switching signal (c) from a control section 15. On the other hand, the signal (a) is inputted to the circuit 8 and a gate 10a, the circuit 108 compares bit data of the signals b1, a and when they are dissident, a dissidence signal (d) is outputted to the control section 15. Moreover, a burst gate signal C1 is inputted to the control section 15. A comparator circuit 19 compares bit data of a reverse sequence PN signal b2 outputted from the reverse sequence FSR 18 and of the signal a1 and outputs a dissidence detection signal (e) to an error measurement section 20 when dissidence to calculate a code error.</p> |
