| 摘要 |
PURPOSE:To detect the data error for memory write by a hardware logic circuit. CONSTITUTION:A CPU 10 outputs write address information ADR and write data DATA to a shared bus SB to write data in a RAM 30. At this time, a control block (CNB) 24 latches write address information ADR and write data DATA in an address latch (L1) 27 and a data latch (L2) 28 respectively. Next, data DATA in the address indicated by write address information ADR is outputted from the RAM 30. A comparison computing element (CMP) 29 compares write data DATA applied to a terminal A and read data applied to a terminal B with each other; and if they do not coincide with each other, an interrupt signal the inverse of INT is made active and is outputted to the CPU 10 to report the occurrence of memory write data error. |
