| 摘要 |
PURPOSE:To hold the reliability of test and to shorten the test time in the address bus test system which tests the address bus to which a memory is connected. CONSTITUTION:A memory 1 is connected to a test function part 4 consisting of a processor or the like through a bus including an address bus 2 and a data bus 3. Data of all '0' is written in the minimum address of the memory 1 by the test function part 4, and data where only one bit '1' is written in addresses having '1' in only one bit, and data is read out from the minimum address. If this data is all '0', it is judged to be normal; but otherwise, '0' stack of the address bit position of '1' is identified. This bit of '1' is succesively shifted to all bit positions of the address bus 2 to perform the '0' stack test. The '1' stack test is performed by the inverted logic. |
