| 摘要 |
PURPOSE:To eliminate limitation being generated during continuous access to the same pattern, in an IC tester and the like, and to obtain a test pattern generator which enables high speed generation of arbitrary test patterns. CONSTITUTION:A bit holding means 3 inputs an LSB of input address by each address cycle and, after holding specific time duration, outputs the LSB to a comparison means 2 of the lowest order bit. The comparison means 2 compares an LSB of the newest address being input with an address LSB of one cycle in advance fed from the comparison means 2 of the lowest order bit, and thereafter signal of specific level determined by whether both bits coincide or not, is output to an access area selection means (consisting of J-K-FF4, an address reverser 5 and FF6). When content of the level signal shows coincidence of both lowed order bits, a different bank from the bank accessed one cycle earlier, is accessed, and when no coincidence, the same bank accessed one cycle earlier accessed. |
