| 摘要 |
An n-stage shift register (sr) has its series input (25) fed with a PDM signal and its clock input fed with a clock signal (cl). A sumner (K3) is fed at its input with n state signals (i41-14i) associated with one of the n register stages to be operated by their states. A low pass filter (tp) has its input fed from the sumner (K3) to provide the mean at the output. A Sigma-Delta modulator may feed the series input (25), and the low-pass be an integrator of the first order, or similar fitter, feeding the modulator input. An intermediate signal may then also feed the integrator so that the time-averaged value of the sumned signals by the PDM-ADC is opposite and equal to the time-averaged intermediate signal. This signal is derived from an analog input.
|
