Process and circuit arrangement for synchronising a signal.

摘要

The invention relates to a device for synchronising an internal signal (Fint) with a reference signal (SYNC), these signals each comprising pulses normally occurring at a nominal frequency. This device comprises: a phase comparator (10); a programmable frequency divider (13); a multiplexer (14) delivering to the divider in order to program it a high binary number (NH) if the comparator is at 1, and a low binary number (NL) if it is at 0; means (34) for storing in sequence the latest states of the comparator; first means of detection (43) for decrementing the high binary number when the latest stored states of the comparator exhibit a single 1 state; and second means of detection (46) for incrementing the low binary number when the latest stored states of the comparator exhibit a single 0 state. <IMAGE>