发明名称 |
Data latch circuit having non-volatile memory cell. |
摘要 |
<p>A data latch circuit comprises a non-volatile memory cell (11) having its threshold voltage changed in accordance with data to be stored therein, and a latch circuit (60). The cell (11) has a transistor (T3) for writing data and a transistor (T4) for reading data. The writing and reading transistors (T3, T4) has a common floating gate. The reading transistor (T4) has a threshold voltage lower than the writing transistor (T3). During normal operation, a ground potential (Vss) is applied to the control gate of the reading transistor (T4). The latch circuit (60) latches data in accordance with whether the non-volatile memory cell (11) is in the on-state or off-state. <IMAGE></p> |
申请公布号 |
EP0525680(A2) |
申请公布日期 |
1993.02.03 |
申请号 |
EP19920112729 |
申请日期 |
1992.07.24 |
申请人 |
KABUSHIKI KAISHA TOSHIBA |
发明人 |
ATSUMI, SHIGERU;BANBA, HIRONORI |
分类号 |
G11C17/00;G06F11/00;G11C8/06;G11C16/04;G11C16/06;G11C29/00;G11C29/04;(IPC1-7):G11C11/417 |
主分类号 |
G11C17/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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