| 摘要 |
PURPOSE:To prevent production of an error in a read data after service-in. CONSTITUTION:First and second delay variable circuits 3,4 delays an input data 1 and a frame pulse 2 by using a delay data 15 to form a write data 5 and a write address initializing pulse 6 respectively. A memory 8 writes the write data 5 and reads the written write data 5 to form a read data 9. A counter 12 counts a time difference between a write address initializing pulse 6 initializing the memory 8 and a read address initializing pulse 10, and a latch circuit 13 latches the count by using out of synchronism recovery information 16. A decode circuit 14 generates the delay data 15 from the latched count so as to maximize the time difference between the write address initializing pulse 6 and the read address initializing pulse 10. |
