| 摘要 |
PURPOSE:To reduce both the resistance and capacitance of a bit line by the use of a planer cell structure. CONSTITUTION:A bit line 4 comprises an N-type diffusion layer 6 divided according to a word line 18 as a unit, and a low resistance wiring 8 which connects a plurality of diffusion layers 6 in the bit line direction. On the diffusion layer 6, an oxide film exists. The diffusion layer 6 and the wiring 8 are connected through an opening 12 in the oxide film. The lower layer of the wiring 8 is formed of a polycrystalline silicon film to which an impurity is introduced, and the upper layer is formed of a tungsten silicide film. The diffusion layer 6 is formed by diffusing an impurity in a substrate 2 from the polycrystalline silicon film of the wiring 8 through the opening 12 in the oxide film 10. The ward line 18 made of the polycrystalline silicon film is formed in the direction orthogonally intersecting the bit line 4 on the substrate 2 through a gate oxide film 14 and between the wiring 8 and the ward line through an oxide film 16. |
