| 摘要 |
PURPOSE:To obtain the PLL lock or unlock detection circuit which can obtain a high-accuracy PLL lock detecting signal and can exclude a smoothing circuit. CONSTITUTION:The lock detecting signal is outputted while receiving a 1/N frequency dividing signal (n) which is outputted from a programmable counter 2 receiving an input signal Fin, signal Fi equivalent to one cycle of the input signal outputted from a flip-flop 3 to receive the input signal Fin, bar Fi' signal delayed for the 1/2 cycle rather than a bar Fi outputted from a flip-flop 4 while receiving the inverted signal of the input signal Fin, and reference frequency signal REF. Therefore, since a PLL lock state can be discriminated by a signal processing like a digital logic circuit, the PLL lock state can be discriminated without being affected by the dispersion of a judge level and without requiring any smoothing circuit. |
