| 摘要 |
PURPOSE:To reduce the size of a PLL circuit configuration for the reproduction of multi-tracks with plural heads by processing the reproduction clock, which is obtained through the PLL, with a phase shifter. CONSTITUTION:Two or plural number of magnetic heads 601 and 602 reproduce two or plural number of channel tracks and the reproduced clock is processed by a PLL, which consists of a phase comparator 13, a loop filter 14 and a VCO 15, through a switch 11. And the output of the PLL is phase shifted by phase shifters D type FF 161 and 162 which correspond to the heads 601 and 602, respectively. Having this configuration, no need to provide a PLL corresponding to a head and a single PLL generates a clock whose phase is matched with the simultaneously reproduced data of multi-tracks. As a result, the size of the PLL circuit configuration, which simultaneously reproduces a clock, is reduced during the simultaneously reproduction of multi-tracks. |
