| 摘要 |
<p>PURPOSE:To improve the data transfer efficiency by reading a data set to a dual port RAM with a CPU so as to transfer the data to a dual port RAM of an opposite package. CONSTITUTION:A CPU 1 of a CPU package 6 outputs an address and a write control signal to ports 2a, 2b of a transmission dual port RAM 2 and a desired data is written in the RAM. The data is read via a transmission sequential address generating circuit 3 asynchronously with the CPU 1 and written in a reception dual port RAM 11 at a transfer destination similar to the RAM 2 of a peripheral device control package via a reception sequential address generating circuit 12 and read therefrom. The data transmission reception from the package 16 to the package 6 is implemented similarly and the CPU has only to set the transfer data, then the load is relieved and the data transfer efficiency is enhanced.</p> |
