发明名称 |
SYNCHRONIZATION STATE DETECTION CIRCUIT |
摘要 |
PURPOSE:To prevent erroneous output of a detection signal representing the synchronization state. CONSTITUTION:A timer section 2 outputs a pulse measurement time set by a time base section 1. An out of synchronism pulse counter 3 and a synchronous pulse counter 4 output respectively an out of synchronism signal and a synchronizing signal when a synchronizing signal pulse inputted in response to the frame synchronization state from an input terminal 8 reaches a set measuring time. An N-time count section 5 outputs the synchronizing signal or the out of synchronism signal received in excess of a preset reference number. A count comparator section 6 upon the simultaneous receipt of the synchronizing signal and the out of synchronism signal from the N-time count section 5 outputs the out of synchronism signal with priority. A selection circuit 7 outputs a synchronization state pulse representing out of frame synchronism when the circuit 7 receives no input of the synchronizing signal and the out of synchronism signal from the count comparator section 6. |
申请公布号 |
JPH0522276(A) |
申请公布日期 |
1993.01.29 |
申请号 |
JP19910168597 |
申请日期 |
1991.07.10 |
申请人 |
NEC CORP;NEC MIYAGI LTD |
发明人 |
TAJIRI MITSUHIRO;ITABASHI SHUNICHI |
分类号 |
H04J3/06;H04L7/00;H04L7/08 |
主分类号 |
H04J3/06 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|