| 摘要 |
PURPOSE:To speed up the addition and subtraction of the floating-point arithmetic unit through the improvement of the mantissa part processing part. CONSTITUTION:This device is provided with a computing element 11 which outputs the addition/subtraction result of mantissa part data ma and mb after preshifting as a 1st intermediate result (intermediate sum) R1, a rounding adder 12 which outputs the rounding addition result of the intermediate sum R1 as a 2nd intermediate result (rounding result) R2, a postshifting counting encoder circuit (PSCE circuit) 13 which outputs information on postshifting to be done for the rounding result R2, and a postshifting circuit 14 which shifts the rounding result R2 actually right or left for normalization. The PSCE circuit 13 is equipped with a shift specification part 15 which specifies the contents of the postshifting corresponding to the position of the 1st non-zero value bit in the intermediate sum R1 and a shift correction part 16 which corrects the shift quantity of the postshifting when the movement of the position of the 1st non- zero value bit for carrying at the time of rounding addition is expected. |
