| 摘要 |
PURPOSE:To reduce the cell area and enhance the integration by a structure wherein there are connected in series a plurality of transistor cells which are provided with two channel regions in the upper and lower parts of one gate electrode, and with the upper and lower source and drain regions which are independent of each other and with the channel region between them, respectively. CONSTITUTION:The channels for a memory cell transistor and a selector transistor are arranged above and below one gate electrode. In other words, a lower transistor group (Qs, Qss2, QM1-QM3) comprising gate electrodes 4a and 4b, and impurity diffusion layers 5a-5c constituting a lower source and drain region placed beneath the electrodes, and an upper transistor group (Qs3, Qs4, QM4-QM6) comprising gate electrodes 4a and 4b, and semiconductor thin films 9 and 10 placed above the electrodes are formed by superposition. Then, in each of the transistor groups, the transistors are connected in series to constitute a transistor block thereby to reduce the cell area to a 50% of the conventional cell area. |
