发明名称 Multi-layer wiring structure in semiconductor device and method for manufacturing the same.
摘要 <p>After an interlayer insulator film (4) is deposited on a wiring conductor (3) formed on a semiconductor device element and is then planarized, a first conducting film (5) and a first insulating film (9) are deposited in that order. Thereafter, a through hole (8) is formed, and a second conducting film (10) and a second insulating film (11) are deposited and then etched back so that these films remain on only a side wall surface of the through hole. The through hole is then filled with a metal plating (Fig. 1D), and the etching-back is performed again. Thereafter, an upper level wiring conductor (7) is plating-grown by supplying an electric current to the first conducting film (5), and the second conducting film (10) remaining on the side wall surface and the lower level wiring conductor (3). Thus, a planarized wiring conductor having only a slight step can be obtained in a process for forming a wiring for a semiconductor device by an electroplating method. <IMAGE></p>
申请公布号 EP0524818(A1) 申请公布日期 1993.01.27
申请号 EP19920306724 申请日期 1992.07.23
申请人 NEC CORPORATION 发明人 MORISHITA, YASUYUKI
分类号 H01L21/3205;H01L21/768;H01L23/522 主分类号 H01L21/3205
代理机构 代理人
主权项
地址