发明名称 RESET SIGNAL WAVEFORM SHAPING CIRCUIT
摘要 PURPOSE:To waveform-shape an input reset signal to a reset signal being a pulse with a prescribed width or over without any chattering by latching the input reset signal for a prescribed time. CONSTITUTION:An integration circuit 3 averages an input to absorb small chattering. In this case, a D-latch logic element 5 is brought into a through-state. Then points F, G are at logical H and a point H rises slowly from a low level to a high level by an integration circuit 6. A point I is at a low level for a time equivalent to the time constant of the circuit 6. Thus, a point J is at a low level for that time. Furthermore, a point L goes to a low level after a tie equivalent to time constant comprising R3 and C2 and an output of the element 5 is latched. Then points I, J, K restore to a high level and the point L goes to a high level and the element 5 restores to the through-state. That is, the output at the point G is fixed and the logic level of the circuit 6, a Schmitt trigger logic element and the point I is fixed. Thus, a pulse without chattering is outputted as a reset signal.
申请公布号 JPH0514145(A) 申请公布日期 1993.01.22
申请号 JP19910162735 申请日期 1991.07.03
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 YOSHII HIROMITSU
分类号 H03K5/1252;H03K5/01 主分类号 H03K5/1252
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