| 摘要 |
PURPOSE:To provide DRAM in which the stabilization of the operation as well as a large scale capacity and a highspeed operation are aimed. CONSTITUTION:Each gate of a first and a second transistor Q10, Q9 are connected to a first bit line 12 (BL) and a second bit line 12 (/BL)that makes a pair with BL, and each drain is connected to a first data line 13 (/DQ) and a second data line 13 (DQ) that makes a pair with /DQ through a third and a fourth transistors Q8, Q7 that are controlled by the selection line 19 of a column which is a first control line. The selection line 19 of the column is decoded by AYn21. The sources of the first and the second transistors Q10, Q9 are commonly grounded, and the gates of a fifth and a sixth transistors Q11, Q12 are connected to the drains of the first and the second transistors Q10, Q9 respectively. The drains of the fifth and the sixth transistors Q11, Q12 are connected to the drains of the second and the first transistors Q9, Q10, and the sources of the fifth and the sixth transistors Q11, Q12 are connected commonly to the selection line 190 of the column. The selection line 190 of the column is decoded by AYm210. |
