| 摘要 |
PURPOSE:To obtain the novel timing recovery circuit in which no identification error is caused by making a relation of a phase between an input data and a clock in an identification circuit stable. CONSTITUTION:An input data is divided into two after through an input buffer 1. The one is inputted for the purpose of clock recovery via a prescribed width pulse generating circuit 4, a narrow band pass filter 5, a delay line 6 and a limit amplifier circuit 8 to a flip-flop 7 of an identification circuit. The other data of the divided input data is inputted to the flip-flop 7 of the identification circuit via an AND gate 4 employed for the prescribed width pulse generating circuit and a similar gate to that of the limit amplifier 8 having an inverter in series thereto. |
