| 摘要 |
<p>PURPOSE: To reduce chip area and enable RAM-to-RAM fast transmission by making two adjacent RAMs share one SRAM. CONSTITUTION: Data transmission transistors(TR) T1-Tn and T'1-T'n which are applied at their gates with block select signals ISO1 and ISO2 are coupled with RAMs I and II, which are coupled with one SRAM through those data transmission TRs T1-Tn and T'1-T'n. Then data transmitted from the RAM I or II is latched by the SRAM in parallel and then outputted as serial output data. Instead of them, data inputted in series are latched by the SRAM, and the data in the SRAM are written to the RAMs I and II through the transmission TRs T1-Tn, and T'1-T'n.</p> |
