| 摘要 |
PURPOSE:To shorten the time till synchronization is established even when the frequency of input occurrence of phase information is low by providing a frequency division ration adjustment circuit storing a phase comparison signal and outputting a phase control signal at a frequency of occurrence based on the result of storage to the relevant circuit. CONSTITUTION:The offset direction of a clock signal with respect to a synchronization object signal from an input terminal 9 is detected by an offset direction detection circuit 4 counting a clock from an oscillation circuit 8 and a phase comparison signal with respect to a frequency division clock from a variable frequency division circuit 7 is outputted by a phase comparator circuit 2. The comparison signal is stored in a frequency division ration adjustment circuit 5 and a frequency division ratio decision circuit 6 is controlled by a 2nd control signal outputted based on the frequency of occurrence of the result of storage of the circuit 5 together with a 1st control signal outputted from a sequential loop filter 3 and the variable frequency division circuit 7 is controlled by a frequency division ratio control signal outputted from the circuit 6. Through the constitution of provision of the frequency division ratio adjustment circuit as above, even when the frequency of input occurrence of phase information is low, the time till the synchronization is established is less and the locking is implemented at a high speed. |
