| 摘要 |
<p>PURPOSE:To accurately hold signal values and also eliminates a conventionally required signal value holding circuit when the power consumption of the digital circuit device is reduced by setting the device in a clock stop state. CONSTITUTION:The digital circuit device is equipped with a clock stop mode setting circuit 70 which outputs a clock stop mode setting signal KS on detecting a holdable state wherein whether or not the variation of a 1st clock signal phi1 of the circuit device having logic circuits 18-20 controlled with input signals 11 and 12 to a 1st potential varies the outputs of 1st transfer gates 50-52 is determined according to the input signals I1 and I2 and a clock control circuit 40 which performs control so that the 1st and 2nd clock signals phi1 and phi2 are not supplied to the 1st and 2nd transfer gates 50-52 and 53-55 according to the clock stop mode setting signal KS and also sets the values of the signals supplied to the transfer gates so that the 1st and 2nd transfer gates 50-52 and 53-55 are opened.</p> |
