| 摘要 |
PURPOSE:To prevent a transmission center frequency from being deviated regardless of a coding rate of a modulation signal by providing a sample-and-hold circuit to a PL loop. CONSTITUTION:A synchronizing signal detection circuit (g) monitors a modulation signal, detects a synchronizing signal sent periodically in a prescribed signal pattern and sends a detection pulse to a PLL control circuit (h). The PLL control circuit (h) measures a prescribed time based on a pulse from the synchronizing signal detection circuit (g) and sends a control signal to a sample- and-hold circuit (i) by a time width of the synchronizing signal in a timing when a succeeding synchronizing signal comes. The sample-and-hold circuit (i) outputs a phase signal from a low pass filter (d) to an adder (a) as it is when the control signal comes from the PLL control circuit (h). When the control signal from the PLL control circuit (h) is stopped, a just preceding phase difference signal is latched and fed to the adder (a). Thus, even when a ratio of 1, 0 in the modulation signal is not impartial, the center frequency of the transmission signal is not deviated. |
