| 摘要 |
PURPOSE:To improve the accuracy and resolution with simple configuration by applying retiming to the dispersion in the delay time caused in a delay circuit with a flip-flop circuit. CONSTITUTION:A reference clock signal SR is frequency-divided by a frequency division circuit 6 into two clock signals S1, S2. A test rate signal Sr is delayed for a time corresponding to an input data D1 in a delay circuit 1. An output S3 of the circuit 1 is subject to complete retiming when it is latched in an FF circuit 2 in a timing of the signal S.. An output S4 of the FF circuit 2 is delayed within one period of the signal S2 by a delay circuit 3 and subject to complete retiming when it is latched in the FF circuit 4 in a timing of the signal S1. An output S6 of the FF circuit 4 is delayed in a delay circuit 5 with further fine resolution corresponding to an input data D3 to be an output S7. Thus, number of expensive ECL circuits is reduced and the timing generating circuit with high accuracy and high resolution is realized with inexpensive configuration. |
