发明名称 |
Static random access memory having Bi-CMOS construction. |
摘要 |
<p>A semiconductor memory of a Bi-CMOS construction is disclosed. The memory includes a plurality of cell blocks connected in common to a pair of main-bit lines. Each of the cell blocks includes a plurality of word lines, a pair of pre-bit lines, a plurality of memory cell each connected to one of the word lines and to the pre-bit lines, and a pair of bipolar transistors having the respective bases connected to the pre-bit lines and the respective collector-emitter current paths connected in series between the main-bit lines. One of the bipolar transistors is turned ON in response to data stored in a selected memory cell to discharge the associated main-bit line. The discharging of the pre-bit line and the main-bit line is thus carried out rapidly to increase data read operation speed. <IMAGE></p> |
申请公布号 |
EP0523756(A2) |
申请公布日期 |
1993.01.20 |
申请号 |
EP19920116920 |
申请日期 |
1987.08.14 |
申请人 |
NEC CORPORATION |
发明人 |
SHIBA, HIROSHI;EGUCHI, SHOJI |
分类号 |
G11C7/18;G11C11/412;G11C11/416;G11C11/419 |
主分类号 |
G11C7/18 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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