Integrated circuit memory device.

摘要

A dual-port memory device provides for a memory array which is divided approximately in half. Between the two halves of the array, a bit line crossover scheme is provided which minimizes stray capacitance and cross-coupling capacitance between bit lines for the two different ports. A bit line layout plan which minimizes such capacitances causes the data for one of the ports to be inverted in one-half of the array. When data from this half of the array is read or written by such port, the data being read or written must be inverted. <IMAGE>