| 摘要 |
The circuit for driving four gray video data through a ECL logic unit at high speed to form the four gray of monochromic image on a high resolution monitor comprises a logic level converter (8) for converting of four pixel video data (TSD0-TSD7) with TTL level into ECL level data, a shift register (10) for storing the ECL level of four pixel video data to convert the pixel data into one pixel data by a shift clock, an oscillator (12) for generating a shift clock (CLK0) to generate a load clock (CLK1) for the register (10), and an OR/NOR gate unit (24) for converting the one pixel data from the register (10) into a four gray and one pixel of ECL video data.
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