| 摘要 |
<p>PURPOSE:To eliminate uneven control in time and to improve the whole processing speed by providing this multiporcessor system with plural communication means for arranging a jump information storing memory for storing jump information obtained at the time of generating a forced interruption in a multi- port memory. CONSTITUTION:A control request from a CPU 1 on the control request side to a CPU 2 on the controlled request side is generated as a reset signal. Namely a forced interruption is reset. Each of a communication means 1a in the CPU 1 and a communication means 2a in the CPU 2 generates a control request from the control request side CPU 1 to the controlled request side CPU 2 or from the CPU 2 to the CPU 1 as a reset and arranges a jump information memory for storing jump information obtained at the time of generating the reset in the multi-port memory 3. When the CPU 1 generates a control request to the CPU 2 as a reset for instance, the CPU 2 is reset and control concerned is started by a jump address stored in a reset vector storing memory in the memory 3. Consequently high-speed forced control can be executed and control with high real time property can be enabled.</p> |
