| 摘要 |
PURPOSE:To obtain the arithmetic circuit improving the utilizing efficiency of a computing element by turning a data input part to a pipe line. CONSTITUTION:Time divided input data are successively separated by multiplexers 1 and 2 based on ENX and ENY and the separated data are held in a temporary multiplicand register 7 and a temporary multiplier register 10. When a multiplication start signal (TRIG) is turned to an ON state, the data (multiplicand) held in the temporary multiplicand register 7 are transferred to a multiplicand register 3 by a multiplexer 8, and the data (multiplier) held in the temporary multiplier register 10 are transferred to a multiplier register 5 by a multiplexer 11. The data from the multiplicand register 3 and the data from the multiplier register 5 are inputted to a multiplier 4 at the same timing, and the multiplier 4 multiplies the multiplier to the multiplicand and obtains a multiplied result. In this case, actual multiplying time is two clocks, a clock frequency can be made double and processing speed can be improved. |
