| 摘要 |
<p>PURPOSE:To provide a chip varistor which prevents the growth of a semiconductor crystal at the time of baking for reducing the variations in varistor voltage and for reducing a lead current that prevents an electric field from concentrating on an end of an electrode for incresing a surge resistance. CONSTITUTION:In a ceramic body 2 which is fabricated by laminating the plurality of semiconductor ceramic layers 7a-7c, a first and a second internal electrode 3, 4 are so buried that they may not overlap each other in the thickness direction 't' of the ceramic layer 7a. Only one end 3a, 4a of each of the first and the second internal electrode 3, 4 is connected to an external electrode 6 which is formed on left and right end faces 2a, 2b of the ceramic body 2. Meanwhile, an unconnected internal electrode 5 not connected to the external electrode 6 is buried in the ceramic body 2 so that it may overlap the first and the second internal electrode 3, 4 through the semiconductor ceramic layer 7a. The first and the second internal electrode 3, 4 and the unconnected internal electrode 5 are installed on different planes. Thus, a chip varistor 1 is fabricated.</p> |
