| 摘要 |
The NAND gate circuit comprises an input stage comprising input resistances (R11,R12), schottky diodes (D11,D12) and bipolar transistors (Q11,Q12) to prevent latch up phenomenon and to clamp input noise, an operating stage comprising P-MOS transistors (Q13,Q14), N-MOS transistors (Q16-Q19) and a ground resistance (R13) to drive output stage according to input signals, and an output stage comprising bipolar transistors (Q15,Q20) to increase output speed and amplifying gain.
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