发明名称 |
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE |
摘要 |
PURPOSE:To achieve a semiconductor integrated circuit device which is suited for a semiconductor memory circuit with a large memory capacity by constituting a delay circuit using a dummy Y selection line. CONSTITUTION:A wiring material which is the same as a Y selection line is used for one end of a generation circuit of a CAS-system Y selection clear signal CE and a dummy YS with a same length is connected. A timing- generation circuit which generates a word clear signal 2B is provided at the other edge side of the dummy YS. A delay circuit is constituted by using this dummy YS and a column reset signal is transmitted, thus forming a reset timing signal of a word line, thus enabling word clear to be performed by setting of a required and minimum time margin since Y reset timing can be known accurately from the dummy Y selection line. |
申请公布号 |
JPH056654(A) |
申请公布日期 |
1993.01.14 |
申请号 |
JP19910040953 |
申请日期 |
1991.02.12 |
申请人 |
HITACHI LTD;HITACHI DEVICE ENG CO LTD |
发明人 |
NOZOE ATSUSHI;MIYAMOTO EIJI;KASAMA YASUHIRO;OSHIMA KAZUYOSHI;TAKAHASHI TSUGIO;YAMAZAKI TAKASHI;SUGA SHINICHI |
分类号 |
G11C11/401;G11C11/407;G11C11/409;H01L21/8242;H01L27/10;H01L27/108;H01L29/78 |
主分类号 |
G11C11/401 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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