| 摘要 |
PURPOSE:To prevent the overlooking of verification for the connection of scan paths and to improve the efficiency in verification by producing automatically a control instruction for simulation to confirm the logical connection of the scan paths and the expected value of the simulation result and comparing the expected value with the actual simulation result. CONSTITUTION:The simulation model of a logic circuit, the wiring order of scan paths, and the information on the control signal which actuates the model are stored in a model information storing means 1. A simulation control instruction output means 2 outputs a control instruction in order to observe the state value of a flip-flop set on a scan path. A simulation executing means 3 performs the simulation of the logic circuit based on the simulation model and the control instruction. An expected value comparing means 5 compares the simulation result with the expected value of the flip-flop obtained by an expected value producing means 4. Then the information on the discordant flip-flops is outputted if no coincidence is obtained between the simulation result and the expected value. |
