发明名称
摘要 <p>PURPOSE:To perform operation dealing with more bits than those of a system without increasing the number of cycles by setting the frequency of the clock in a CPU to an integral multiple of the clock frequency of a peripheral circuit. CONSTITUTION:The CPU consists of a controller 1 having a sequence circuit, instruction register 2, ALU (arithmetic logical unit) 3, a group of registers 4a- 4i, etc. The operation of the ALU3 is performed by a control signal generated on the basis of an operation clock phic supplied form a signal generating circuit 8 to the controller 1. The frequency of said operation clock signal, i.e. clock signal phic is set to an integral multiple of the frequency of system clock signal Pc1- Pc3 supplied from the signal generating circuit 8 to peripheral circuits of the CPU such as an ROM5, RAM6, and I/O port 7.</p>
申请公布号 JPH053015(B2) 申请公布日期 1993.01.13
申请号 JP19820048888 申请日期 1982.03.29
申请人 HITACHI SEISAKUSHO KK;HITACHI MAIKURO KONPYUUTA ENJINIARINGU KK 发明人 OOCHI ATSUSHI
分类号 G06F9/30;G06F1/04;G06F1/08;G06F15/78 主分类号 G06F9/30
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