| 摘要 |
<p>This variable clock dividing circuit is provided with n dividers (31-34) including the first divider (31) to divide the basic clock (10) by a predetermined dividing ratio and the n-th divider to branch and input the output from the (n-1)th divider and selectively outputs one of the clocks output from the dividers using a switching circuit (40). A divider is, on the input side, provided with a phase synchronization circuit (20) to synchronize the phase of the clock input to n dividers based on the basic clock (10). The phase synchronization circuit (20) comprises a buffer (21) to input the basic clock (10) with a delay to the first divider and a plurality of AND gates (22-24) each corresponding to the second to the n-th dividers and inputs the basic clock and the outputs from all the dividers up to the previous stages to the AND gates (31-34). <IMAGE></p> |
