| 摘要 |
<p>An apparatus for processing a video image which can magnify or compress a video image in the vertical direction arbitrarily. The horizontal synchronizing signal (HS) of a video image signal (CS) is inputted at the reference input terminal (63a) of a phase comparator (63) in a PLL circuit (62). A clock signal (CK) whose frequency is N1-times as large as that of the signal (HS), is taken out. The frequency of the signal (CK) is reduced to 1/N2 by a frequency demultiplier (67). Since the number N2 is equal to the number of horizontal synchronizing signals in a vertical synchronizing period, the number of sampling lines in the vertical direction is N1. Therefore, when using the output signal (a line clock signal LCK) of the frequency demultiplier (67) as the signal for the increment of the vertical address of a video image memory (70), the video image can be magnified or compressed according to the magnitude of the number N1 which is variable. <IMAGE></p> |
