| 摘要 |
A processor having a plurality of windowed registers comprising IN, OUT and local window registers, where the IN registers of each window are addressable as the OUT registers of a logically-adjacent succeeding window. The processor also having a cache of two sets of IN/OUT registers with switchable addresses and a set of local cache registers. The addresses of the first set of IN/OUT registers can be changed to the addresses of the second set of IN/OUT registers, and vice versa, when the current window changes during a save or restore operation.
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